1. Field of the Invention
The present invention relates to a semiconductor device utilizing a wiring tape, such as BGA (Ball Grid Array) or CSP (Chip Size Package).
2. Description of the Related Art
In recent years, there have been growing demands for the increased number of pins and a miniaturization with regard to semiconductor devices. To meet the demand, there have been proposed semiconductor devices called BGA or CSP. An example of such a semiconductor device is disclosed in Japanese Patent Laid-Open No. 55447/1997.
FIGS. 1A to 1C show the disclosed semiconductor device, FIG. 1A is a vertical sectional view taken along a line C-C' of FIG. 1B, FIG. 1B is a horizontal sectional view taken along a line A-A' of FIG. 1A, and FIG. 1C is a horizontal sectional view taken along a line B-B' of FIG. 1A.
As shown in FIGS. 1A to 1C, the disclosed semiconductor device has a construction that an electrode 101a of semiconductor integrated circuit element (hereinafter referred to as chip) 101 is connected to an inner lead 102f extending inside a frame portion of a TAB tape 102, which in turn is adhered to a metallic support frame 107, and chip 101, both oh which are covered with a potting resins 106. TAB tape 102 has a circuit pattern 102a and inner lead 102f which are formed by etching metallic foil adhered onto a base substrate (e.g., polyimide tape) 102c of a frame configuration. Circuit pattern 102a is covered with a cover resist 102e except a portion to be connected with an external terminal 104.
In the above structure, the provision of a through hole for the connection between external terminal 104 and a support frame 107 in the frame portion of TAB tape 102, will endow support frame 107 with a GND plane (ground plane) function.
Another semiconductor device such as shown in each of FIGS. 2A to 2C has been proposed. FIG. 2A is a vertical sectional view taken along a line C-C' of FIG. 2B, FIG. 2B is a horizontal sectional view taken along a line A-A' of FIG. 2A, and FIG. 2C is a horizontal sectional view taken along a line B-B'.
The semiconductor device comprises a chip 201, a single-layer wiring tape 202 and a molding resin 203 for maintaining an outer shape of the device. Chip 201 includes an internal electrode 201a which is connected to an external terminal (e.g., solder ball) 204, via through hole 202b in a base substrate 202c of a wiring tape 202, and a circuit pattern 202a on base substrate 202c. Circuit pattern 202a is covered with a cover resist 202e except a portion to be connected with external terminal 204 and a portion forming through hole 202b. Electrode 201a on chip 201 and through hole 202b of wiring tape 202 are connected to each other by a bump. This connecting method is called an inner bump bonding (IBB) method. Wiring tape 202 and chip 201 are closely bonded to each other with an adhesive material 202d provided in wiring tape 202 by employing a hot pressing method. Chip 201 is covered by a molding resin 203 which is formed by employing a transfer molding method.
Unlike the semiconductor device described in the foregoing publication which uses TAB tape, the above structure enables external terminals to be arranged even on an area occupied by the chip, thus making a length of a wiring pattern for the connecting between the internal electrode and the external terminal shorter. This result in improved electrical characteristics as well as improved characteristics of radiating heat to a mounted substrate. In addition, unlike the inner lead of TAB tape, the external terminals can be freely arranged.
An approach to improve electrical characteristics such as noise reduction in the semiconductor device shown in FIGS. 2A to 2C, is that GND plane or power plane is provided on an outer periphery of base substrate 202c of wiring tape 202, and a wiring pattern is provided from a ground electrode on chip 201 to the GND plane(or from a power electrode on the chip to the power plane), passing between pads to be connected with the external signal terminal.
However, a further increase in the number of pins causes a pitch between the pads to be connected with the external signal terminal to be smaller. Thus, there is a limit on the number of wiring patterns which can be passed between the pads, making it difficult to provide the wiring pattern for GND and the wiring pattern for a power source between the pads. Namely, when the number of pins further increases, improvement of electrical characteristics such as noise reduction may be impossible.
An approach to address the above problem may involve a multilayer structure of a wiring tape, that is, a signal layer, a GND layer, and a power layer. This approach is, however, disadvantageous in that a multilayered wiring tape is costly, and hence reducing the cost of products may be impossible.